Csynthesis

SCPI Commands :

CSYNthesis:OTYPe
CSYNthesis:STATe
CSYNthesis:VOLTage

class CsynthesisCls[source]

Csynthesis commands group definition. 13 total commands, 4 Subgroups, 3 group commands

get_otype() → ClkSynOutType[source]

# SCPI: CSYNthesis:OTYPe
value: enums.ClkSynOutType = driver.csynthesis.get_otype()

Defines the shape of the generated clock signal.

return:

mode: SESine| DSQuare| CMOS| DSINe SESine = single-ended sine DSINe = differential sine DSQuare = differential square CMOS = CMOS

get_state() → bool[source]

# SCPI: CSYNthesis:STATe
value: bool = driver.csynthesis.get_state()

Activates the clock synthesis.

return:

state: 1| ON| 0| OFF

get_voltage() → float[source]

# SCPI: CSYNthesis:VOLTage
value: float = driver.csynthesis.get_voltage()

Sets the voltage for the CMOS signal.

return:

voltage: float Range: 0.8 to 2.7

set_otype(mode: ClkSynOutType) → None[source]

# SCPI: CSYNthesis:OTYPe
driver.csynthesis.set_otype(mode = enums.ClkSynOutType.CMOS)

Defines the shape of the generated clock signal.

param mode:

SESine| DSQuare| CMOS| DSINe SESine = single-ended sine DSINe = differential sine DSQuare = differential square CMOS = CMOS

set_state(state: bool) → None[source]

# SCPI: CSYNthesis:STATe
driver.csynthesis.set_state(state = False)

Activates the clock synthesis.

param state:

1| ON| 0| OFF

set_voltage(voltage: float) → None[source]

# SCPI: CSYNthesis:VOLTage
driver.csynthesis.set_voltage(voltage = 1.0)

Sets the voltage for the CMOS signal.

param voltage:

float Range: 0.8 to 2.7

Cloning the Group

# Create a clone of the original group, that exists independently
group2 = driver.csynthesis.clone()

Subgroups